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232 articles for “Low-power”
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Research ArticleOpen accessEvery word in the titlePERFORMANCE ANALYSIS OF HIGH EFFICIENCY LOW DENSITY PARITY-CHECK CODE DECODER FOR LOW POWER APPLICATIONSM. Revathy, R. SaravananIn this study, we propose a low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection and correction applications. LDPC codes have been adopted in latest wireless standards such as satellite and mobile communications since they possess superior error-detecting and correcting capabilities. As technology scales, memory devices become larger and more powerful and low power consumption … …American Journal of Applied Sciences, Vol. 11, Issue 4 · 30 Jan 2014 · 6,882 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleUltra Low Power Single Edge Triggered Delay Flip Flop Based Shift Registers Using 10-Nanometer Carbon Nano Tube Field Effect TransistorRavi Thiyagarajan, Kannan VeerappanCarbon Nano Tube Field Effect Transistor is currently considered as promising successor of Metal Oxide Semiconductor Field Effect Transistor. The scaling down of the Metal Oxide Semiconductor device faced serious limits like short channel effect, tunnelling through gate oxide layer, associated leakage currents and power dissipation when its dimension shrink down to 22 nanometer range. Further scaling of Metal Oxide … …American Journal of Applied Sciences, Vol. 10, Issue 12 · 14 Oct 2013 · 6,749 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,155 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band ZigbeeNesreen Mahmoud Hammam Ismail, Masuri OthmanProblem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,057 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleComparative Studies on the Performance of Low Power Transmitters for Wireless Sensor NodesT. Sasilatha, J. RajaProblem statement: Power consumption was one of the most challenging aspects to design low power wireless sensor nodes. The objectives of the study were to (i) Design low voltage, low power transmitters for wireless sensor nodes and (ii) Compare and analyze the performance of the transmitters. Approach: The transmitters employed direct digital modulation scheme to reduce the power consumption of … …Journal of Computer Science, Vol. 5, Issue 2 · 28 Feb 2009 · 7,450 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Power Hardware Implementation of High Speed FFT CoreM. Kannan, S. K. SrivatsaApplications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift … …Journal of Computer Science, Vol. 3, Issue 6 · 30 Jun 2007 · 7,227 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of a Single-Phase Rectifier with Improved Power Factor and Low THD using Boost Converter TechniqueIsmail Daut, Rosnazri Ali, Soib TaibThe method of using Boost type of converter was proposed for a 300W single-phase rectifier in this paper. By designing the necessary techniques and methodology, the overall Power Factor (PF) and Total Harmonic Distortion would be improved to the expectation. The cause of having low PF and high THD for a diode-capacitor type of rectifiers is related to non-linearity of … …American Journal of Applied Sciences, Vol. 3, Issue 9 · 30 Sep 2006 · 7,127 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Low Cost Design Solution - DSP Based Active Power Factor Corrector for SMPS/ UPS( Single Phase)Samia Pillai Pitchai, B. UmamaheswariAs per international agency regulation (IEC 1000-3-2/EN 61000-3-2) and market expectation, it is important to reduce current harmonics in the AC line current drawn by SMPS/ UPS connected to AC Mains as source and also it is desired by the user to deliver maximum power output by achieving unity power factor. To achieve the above objectives in SMPS/ UPS, APFC … …American Journal of Applied Sciences, Vol. 3, Issue 1 · 31 Jan 2006 · 6,896 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Power Multiplier by Effective Capacitance ReductionNageshwar Reddy Peddamgari, Damu RadhakrishnanIn this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 22 Feb 2017 · 7,462 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleCoupling Routing Algorithm and Data Encoding for Low Power Networks on ChipMaurizio Palesi, Davide Patti, Giuseppe Ascia et al.The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the functional and non functional indices of the overall system. Traditionally, routing algorithms have been designed considering performance and cost as the main objectives. In this study we focus on two important non functional metrics, namely, power dissipation and energy consumption. We propose a selection policy … …Journal of Computer Science, Vol. 11, Issue 3 · 4 May 2015 · 6,928 accessesView PDFCite