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45 results for “FPGA implementation”
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Research ArticleOpen accessIn the abstractOptimised Implementation of Dense Stereo Correspondence for Resource Limited HardwareDeepambika Vadekkettathu Anirudhan, Malangai Abdul RahimanComputer stereo vision is a passive sensing technique that helps to recover 3D information of an environment from 2D images. The stereo correspondence is a challenging task that finds out matching pixels between the stereo image pair based on Lambertian criteria and its result is a disparity space image. The depth of the objects from the camera can be calculated … …Journal of Computer Science, Vol. 14, Issue 10 · 18 Oct 2018 · 7,326 accessesView PDFCite
Research ArticleOpen accessIn the abstractSoftware Defined Radio Implementation of a QPSK Modulator/Demodulator in an Extensive Hardware Platform Based on FPGAs Xilinx ZYNQSérgio Bimbi Junior, Vitor Chaves de Oliveira, Gunnar Bedicks JuniorSoftware Defined Radio (SDR) technology enables wireless devices deployment with support to multiple interfaces in modulation formats and it has gained importance due to the current wireless standards proliferation. In order to activate these functionalities it is necessary to apply SDR inside a reconfigurable hardware such as the Field Programmable Gate Array (FPGA). In this study, design procedures developments are … …Journal of Computer Science, Vol. 11, Issue 4 · 2 Jun 2015 · 8,813 accessesView PDFCite
Research ArticleOpen accessIn the abstractSOPC BASED WIRELESS REMOTE PATIENT MONITORING USING ULTRA LIGHTWEIGHT CRYPTOGRAPHYA. Arun, P. Nirmal KumarRemote Patient Monitoring (RPM) provides flexible and powerful patient surveillance through wearable devices at anytime and anywhere. This can be achieved by using a Body Sensor Network (BSN), which is deployed on a human body for monitoring the healthcare. The mobile healthcare management with increased feasibility and handiness introduced several noteworthy challenges for the provider, policy makers, patient and hospitals. … …Journal of Computer Science, Vol. 10, Issue 10 · 8 May 2014 · 7,194 accessesView PDFCite
Research ArticleOpen accessIn the abstractApplication Specific Integrated Circuits Design and Implementation of Rademacher and Walsh FunctionsA. Abbasi, A. R.M. Alamoud, S. A. AbbasiThe orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP). Today’s DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell … …American Journal of Engineering and Applied Sciences, Vol. 6, Issue 4 · 7 Jan 2014 · 7,340 accessesView PDFCite
Research ArticleOpen accessIn the abstractDESIGN AND IMPLEMENTATION OF GLOBAL POSITIONING SYSTEM RECEIVER IN FIELD PROGRAMMABLE GATE ARRAY WITH SHORT MESSAGE SERVICEGovindaraju Kavya, Vittal Thulasi BaiIn recent years, survival rate from myocardial infarction and bundle branch block has been increased due to the advancements in medical field. Continuous monitoring and location management of these patients becomes an essential task. Hence this study aims in design and development of GPS in a Field Programmable Gate Array (FPGA) and interfaced with a GSM modem to transmit the … …Journal of Computer Science, Vol. 10, Issue 1 · 12 Nov 2013 · 7,563 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Architecture of Maximum Power Point Tracking for Ultra-Low-Power Based Hybrid Energy Harvester in Ubiquitous Devices: A ReviewMichelle Lim Sern Mi, Sawal Hamid Muhammad Ali, Md Shabiul IslamThis research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome … …American Journal of Applied Sciences, Vol. 10, Issue 10 · 6 Sep 2013 · 7,155 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate ArrayMuhammad Ibn Ibrahimy, Rezwanul Ahsan, Iksannurazmi Bambang SoerosoThere are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 28 May 2013 · 6,512 accessesView PDFCite
Research ArticleOpen accessIn the abstractReconfigurable Hardware Architecture for Network Intrusion Detection SystemA. Kaleel Rahuman, G. AthishaIntrusion rule processing in reconfigurable hardware enables intrusion detection and prevention. The use of reconfigurable hardware for network security applications has great strides as Field Programmable Gate Array (FPGA) devices have provided larger and faster resources. This proposes architecture called “BV-TCAM” is presented, which is implemented for an FPGA-based Network Intrusion Detection Systems (NIDS). The BV-TCAM architecture combines the Ternary … …American Journal of Applied Sciences, Vol. 9, Issue 10 · 16 Aug 2012 · 6,981 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Field Programmable Gate Array Based Emulators for Motor Control ApplicationsAhmed Ben Achballah, Slim Ben Othman, Slim Ben SaoudProblem statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important time consuming stage in a design flow. High Level Synthesis technique avoids this bottleneck and increases design productivity as witnessed by industry specialists. Approach: This study proposes to … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 12 Jun 2012 · 8,723 accessesView PDFCite
Research ArticleOpen accessIn the abstractDynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive ImplementationHedi Abdelkrim, Slim Ben Othman, Ahmed Karim Ben Salem, Slim Ben SaoudProblem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using … …American Journal of Engineering and Applied Sciences, Vol. 5, Issue 1 · 18 Feb 2012 · 8,978 accessesView PDFCite