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Research Article · Open access · Published 28 February 2008

FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

A. Senthilkumar, A. M. Natarajan
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Citing articles (2)

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  1. doi:10.7763/ijcte.2013.v5.707Found 12 June 2020
  2. doi:10.1049/iet-spr.2013.0153Found 12 June 2020