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Research ArticleOpen accessDesign For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access MemoryN. M. Sivamangai, GunavathiProblem statement: As technology scales down, the integration density of transistors increases and most of the power is dissipated as leakage. Leakage power reduction is achieved in Static Random Access Memory (SRAM) cells by increasing the source voltage (source biasing) of the SRAM array. Another promising issue in nanoscaled devices is the process parameter variations. Due to these variations, higher … …Journal of Computer Science, Vol. 7, Issue 8 · 15 Jul 2011 · 6,505 accessesView PDF Cite