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1 article for “Pipelined digit-slicing multiplier-less”
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Research ArticleOpen accessIn the keywordsOn-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform ArchitectureYazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman et al.Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 30 Nov 2010 · 8,016 accessesView PDFCite