4 articles for “Low Duty Cycle”

Set a search alert

Research ArticleOpen accessIn the keywordsBit Error Rate Analysis of RS (7, 3) Coded Frequency Shift Keying Using SimulinkT.A. Shanmugasundaram, V. VijayabaskarBit Error Rate is an essential parameter to quantize the effectiveness of transceiver circuits used in low power, low duty cycle sensor nodes. BER can figure out their performance in terms of number of retransmissions, which keeps the node to consume its battery power undesirably rather than conserving it. Forward Error Correction schemes ensure the transceiver circuit to effectively perform … …American Journal of Applied Sciences, Vol. 12, Issue 2 · 25 Mar 2015 · 7,047 accessesView PDF Cite

Research ArticleOpen accessIn the abstractControl Strategy for Discontinuous Conduction Mode Boost Rectifier with Low Total Harmonic Distortion and Improved Dynamic ResponseH.S. AthabDue to its simplicity, the discontinuous conduction mode boost rectifier is potentially the least expensive active line-harmonics reducing circuit. Problem statement: The line current however, shows considerable distortion when the peak input voltage is close to the output voltage, As a result, the input power factor is poor. This study proposes a simple, low-cost method to reduce the line harmonics. … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 4 · 31 Dec 2008 · 7,418 accessesView PDF Cite

Research ArticleOpen accessIn the abstractHarmonics Study and Comparison of Z-source Inverter with Traditional InvertersB. Justus Rabi, R. ArumugamThis paper presents an Impedance Source Inverter for A.C electrical drives. The impedance source inverter employs a unique impedance network cable with inverter main circuit and rectifier. By controlling the shoot-through duty cycle, the z-source inverter system using MOSFETS provide ride-through capability during voltage sags, reduces line harmonics, improves power factor and high reliability, and extends output voltage range. Analysis, … …American Journal of Applied Sciences, Vol. 2, Issue 10 · 31 Oct 2005 · 7,281 accessesView PDF Cite

Research ArticleOpen accessAll words, across the recordHigh Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise ReductionT. S. Karthik, V. Jawahar Senthil KumarProblem statement: In any multimedia processor, controller may consume most of the on-chip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications … …Journal of Computer Science, Vol. 8, Issue 3 · 6 Jan 2012 · 7,172 accessesView PDF Cite