6 articles for “CMOS layout”

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Research ArticleOpen accessIn the keywordsOn-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDMRozita Teymourzadeh, Yazan Samir Algnabi, Nooshin Mahdavi, Masuri Bin OthmanProblem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 7,924 accessesView PDF Cite

Research ArticleOpen accessIn the keywordsSource Couple Logic (SCL): Theory and Physical DesignMohamed Azaga, Masuri OthmanThis study describes and presents the analysis for the Source-Coupled Logic (SCL) inverter as will as the effect of submicron layout parasitics. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics and the effect of noise margin. The inverter gate delay model is … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 1 · 31 Mar 2008 · 7,466 accessesView PDF Cite

Review ArticleOpen accessIn the abstractArchitecture of an Ultra-Low-Power Fully Autonomous Universal Power Conditioner of Energy Harvester for Wireless Sensor Networks: A ReviewYeo Kim Heng, Md. Shabiul Islam, Susthitha Menon et al.A fully autonomous Universal Power Conditioner (UPC) that can accept energy from any micro-energy harvester (e.g., photovoltaic, thermoelectric, electromagnetic, piezoelectric etc.) is proposed. Generally, UPC removes the need of multiple optimized source specific converters. But, the proposed UPC architecture will be Ultra-Low-Power (ULP) with maximized efficiency to support the low energy levels generated by harvesting sources. This UPC uses a … …American Journal of Applied Sciences, Vol. 13, Issue 3 · 28 Mar 2016 · 7,782 accessesView PDF Cite

Research ArticleOpen accessIn the abstractA Novel Architecture of Maximum Power Point Tracking for Ultra-Low-Power Based Hybrid Energy Harvester in Ubiquitous Devices: A ReviewMichelle Lim Sern Mi, Sawal Hamid Muhammad Ali, Md Shabiul IslamThis research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome … …American Journal of Applied Sciences, Vol. 10, Issue 10 · 6 Sep 2013 · 7,155 accessesView PDF Cite

Research ArticleOpen accessIn the abstractLow Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band ZigbeeNesreen Mahmoud Hammam Ismail, Masuri OthmanProblem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,057 accessesView PDF Cite

Research ArticleOpen accessAll words, across the recordVLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless ReceiversRozita Teymourzadeh, Yazan Samir Algnabi, Masuri Othman et al.Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,815 accessesView PDF Cite