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62 results for “FPGA”
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Research ArticleOpen accessIn the keywordsReconfigurable Elliptic Curve Crypto-Hardware Over the Galois Field GF(2163)Mohamed Abdelkader Bencherif, Hamid Bessalah, Abderrezak GuessoumProblem statement: In the last decade, many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware. That is, finding an optimal solution to the one … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,346 accessesView PDFCite
Research ArticleOpen accessIn the keywordsConfigurable Multirate Filter BanksAli Al-HajMultimedia communications require efficient and real-time implementations of multirate digital signal processing systems. The backbone structures of multirate systems are digital multirate filter banks. Therefore, efficient multimedia communications rely, in the first place, on real-time implementations of multirate filter banks. In this paper, we describe a Field Programmable Gate Array (FPGA) implementation of the analysis and synthesis filter banks which … …American Journal of Applied Sciences, Vol. 5, Issue 7 · 31 Jul 2008 · 6,379 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of a Neural Networks Classifier for Face DetectionF. Smach, M. Atri, J. Mitéran, M. AbidFace detection and recognition has many applications in a variety of fields such as security system, videoconferencing and identification. Face classification is currently implemented in software. A hardware implementation allows real-time processing, but has higher cost and time to-market. The objective of this work was to implement a classifier based on neural networks MLP (Multi-layer Perception) for face detection. The … …Journal of Computer Science, Vol. 2, Issue 3 · 31 Mar 2006 · 6,885 accessesView PDFCite
Research ArticleOpen accessIn the keywordsCARRY SAVE COMMON MULTIPLICAND MONTGOMERY FOR RSA CRYPTOSYSTEMRupali Verma, Maitreyee Dutta, Renu VigRSA public key cryptosystem provides encryption and digital signatures. With growth of key size an efficient design of RSA in terms of area, frequency, throughput and power consumption is hard to achieve. Also with the different type of attacks possible, a need for secure RSA cryptosystem which is attack resistant has arisen. This study presents RSA design with Montgomery powering … …American Journal of Applied Sciences, Vol. 11, Issue 5 · 8 Mar 2014 · 6,969 accessesView PDFCite
Research ArticleOpen accessIn the keywordsEfficient Implementation of Stochastic Computing Based Deep Neural Network on Low Cost Hardware with Saturation ArithmeticSunny Bodiwala, Nirali NanavatiThis study presents an efficient and rapid implementation of Stochastic Computing (SC) based Deep Neural Network (DNN) on a low-cost hardware platform. The proposed technique uses bipolar signal encoding in stochastic computing which relatively gives low hardware footprint compared to binary computing. Thereinafter, stochastic max function is presented and subsequently used to approximate the hyperbolic tangent activation function in SC. … …Journal of Computer Science, Vol. 16, Issue 11 · 17 Nov 2020 · 6,875 accessesView PDFCite
Research ArticleOpen accessIn the keywordsThe Optimal Implementation of a Generator of SinusoidSouhila Boudjema, Kaddour SaouchiThe embedded systems occupy a place increasingly important in our daily life. In recent years much of research it is focused on the miniaturization of the various electronic devices. In this study we present the architecture of a digital generator of frequency based on trigonometrically algorithm to obtain sample high frequencies. We treat a comparative study between various processors CORDIC: … …American Journal of Applied Sciences, Vol. 12, Issue 8 · 17 Sep 2015 · 6,292 accessesView PDFCite
Research ArticleOpen accessIn the keywordsTesting Virtual Reconfigurable Circuit Designed For A Fault Tolerant SystemP. Nirmal Kumar, S. Anandhi, M. Elancheralathan, J. Raja Paul PerinbamThis research describes about the testing of virtual reconfigurable circuit (VRC) designed and implemented for a fault tolerant system which averages the (three) sensor inputs. The circuits that are to be tested are those which are successfully evolved in this system under different situations such as (i) all the three sensors are faultless (ii) one of the input sensor fails … …Journal of Computer Science, Vol. 3, Issue 12 · 31 Dec 2007 · 6,854 accessesView PDFCite
Review ArticleOpen accessIn the abstractArchitecture of Ultra Low Power Micro Energy Harvester Using RF Signal for Health Care Monitoring System: A ReviewFarah Fatin Zulkifli, Jahariah Sampe, Muhammad Shabiul Islam, Mohd Ambri MohamedThis research presents architecture of Ultra Low Power (ULP) Micro Energy Harvester (MEH) using Radio Frequency (RF) signal as an input. RF has many advantages compared to other ambient sources because it is not affected by changes of weather or time, does not require heat or wind exposure and it can be moved randomly within the bound of the transmission … …American Journal of Applied Sciences, Vol. 12, Issue 5 · 7 Jul 2015 · 6,956 accessesView PDFCite
Research ArticleOpen accessIn the abstractDelay and Power Reduction in New Routing FabricsS. Vijayakumar, J. Sundararajan, P. Kumar, K. NithyaIn this study we created a new routing fabric for reducing power and delay. The power consumed in a FPGA core consists of both static and dynamic components. Static power contributes only 10% of the total power consumed in a FPGA. On the other hand, dynamic power contributes over 90% of the total power consumed and it is the main … …American Journal of Applied Sciences, Vol. 10, Issue 12 · 23 Oct 2013 · 6,449 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate ArrayMuhammad Ibn Ibrahimy, Rezwanul Ahsan, Iksannurazmi Bambang SoerosoThere are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 28 May 2013 · 6,512 accessesView PDFCite