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144 results for “Delay Performance”
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Research ArticleOpen accessIn the abstractA Novel Interconnect Structure for Elmore Delay Model with Resistance-Capacitance-Conductance SchemeUma Ramadass, Krishnappriya, Jebashini Ponnian, P. DhavachelvanIn this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The RCG model … …American Journal of Applied Sciences, Vol. 10, Issue 8 · 24 Jul 2013 · 7,054 accessesView PDFCite
Research ArticleOpen accessIn the abstractMultichannel Cognitive Cross Layer Optimization for Improved Video TransmissionMeenakshi Murugappan, Manimekalai Thirunavukkarasu, Maneesha S. MohanMultimedia applications particularly real-time video transmission in wireless networks, envisions end to end user perceived video quality as an important QoS parameter to be achieved. Cognitive Radio promising efficient spectrum utilization combined with Cross layer optimization is seen as a powerful combination to achieve the desired video quality. This study proposes Optimal Channel Sensed Multichannel Cognitive MAC (OCSM-CMAC), a QoS … …Journal of Computer Science, Vol. 9, Issue 1 · 6 Feb 2013 · 7,202 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,187 accessesView PDFCite
Research ArticleOpen accessIn the abstractMulticost Routing Approach in Wireless Ad hoc NetworksD. Loganathan, P. RamamoorthyProblem statement: A Wireless ad hoc network is a collection of autonomous movable nodes that communicate with each other over wireless links without any static infrastructure. In these networks there is no fixed topology because of the mobility of nodes, interference, multipath propagation and path loss. A variety of routing protocols and algorithm with varying network settings are analyzed to … …Journal of Computer Science, Vol. 8, Issue 10 · 30 Aug 2012 · 6,739 accessesView PDFCite
Research ArticleOpen accessIn the abstractEnd to End Delay Improvement in Heterogeneous Multicast Network using Genetic OptimizationV. Chandrasekar, K. BaskaranProblem statement: Multicast is a concept of group communication which refers to transmitting the same data or messages from a source to multiple destinations in the network. This one-to-many group communication is a generalization of the concepts of one-to-one unicast and one-to-all broadcast. To deliver data from the sender to all receivers efficiently, routing plays an important role in multicast … …Journal of Computer Science, Vol. 8, Issue 9 · 13 Aug 2012 · 6,737 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous CircuitsD. Jayanthi, M. RajaramProblem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jun 2012 · 7,084 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of an Error Tolerant AdderA. N. Jayanthi, C. S. RavichandranProblem statement: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy and at the same time achieve tremendous improvements in both the power consumption … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 13 Mar 2012 · 7,256 accessesView PDFCite
Research ArticleOpen accessIn the abstractAn Interaction between Congestion-Control Based Transport Protocols and Manet Routing ProtocolsKhuzairi Mohd Zaini, Adib M. Monzer Habbal, Fazli Azzali et al.Problem statement: Although many efforts have been done on studying the behaviour of TCP in MANET, but the behaviour of TFRC remain unclear in MANET. The purpose of this research is two folds. First, we studied the behaviour of TFRC and TCP over AODV and DSR as the underlying routing protocols in terms of throughput, delay and jitter. The second … …Journal of Computer Science, Vol. 8, Issue 4 · 28 Jan 2012 · 7,160 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Transmitter for CDM Based 2×2 Multiple Input Multiple Output Channel Sounder for Multipath Delay MeasurementM. Habib Ullah, M. T. Islam, Mandeep Sing et al.Problem statement: Multiple Input Multiple Output (MIMO) wireless communication system is an innovative solution to improve the bandwidth efficiency by exploiting multipath-richness of the propagation environment. The degree of multipath-richness of the channel will determine the capacity gain attainable by MIMO deployment. Approach: Therefore, it is very important to have accurate knowledge of the propagation environment/radio channel before MIMO implement. … …American Journal of Applied Sciences, Vol. 9, Issue 1 · 24 Nov 2011 · 7,903 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,159 accessesView PDFCite