Sign inSubmit
Tips: “quotes” for a phrase · author:Lee · a DOI goes straight to its article

45 articles for “FPGA implementation”
Set a search alert
Research ArticleOpen accessIn the abstractOn-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDMRozita Teymourzadeh, Yazan Samir Algnabi, Nooshin Mahdavi, Masuri Bin OthmanProblem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 7,924 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Array -Based System-on-Chip for Real-Time Power Process ControlAhmed Karim Ben Salem, Slim Ben Othman, Slim Ben SaoudProblem Statement: Nowadays Real-Time (RT) embedded control applications require not just higher performance but more flexibility as well without increasing cost and resources. Approach: In this study we presented a promising co-design and implementation of control solution. We developed flexible solution using software control algorithms coupled with an embedded RT kernel on powerful embedded processor cores, combined with reconfigurable logic … …American Journal of Applied Sciences, Vol. 7, Issue 1 · 31 Jan 2010 · 7,455 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Array-Based Pulse-Width Modulation for Single Phase Active Power FilterN. A. Rahim, Z. IslamProblem statement: The design and implementation of a sinusoidal Pulse-Width Modulation (PWM) generator for a single-phase hybrid power filter is presented. Approach: The PWM was developed in an Altera® Flex 10 K Field Programmable Gate Array (FPGA) and the modulation index was selected by calculating the DC bus voltage of the active filter through a digital controller, by Proportional-Integral-Derivative (PID) … …American Journal of Applied Sciences, Vol. 6, Issue 9 · 30 Sep 2009 · 7,293 accessesView PDFCite
Research ArticleOpen accessIn the abstractReconfigurable Elliptic Curve Crypto-Hardware Over the Galois Field GF(2163)Mohamed Abdelkader Bencherif, Hamid Bessalah, Abderrezak GuessoumProblem statement: In the last decade, many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware. That is, finding an optimal solution to the one … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,346 accessesView PDFCite
Research ArticleOpen accessIn the abstractConfigurable Multirate Filter BanksAli Al-HajMultimedia communications require efficient and real-time implementations of multirate digital signal processing systems. The backbone structures of multirate systems are digital multirate filter banks. Therefore, efficient multimedia communications rely, in the first place, on real-time implementations of multirate filter banks. In this paper, we describe a Field Programmable Gate Array (FPGA) implementation of the analysis and synthesis filter banks which … …American Journal of Applied Sciences, Vol. 5, Issue 7 · 31 Jul 2008 · 6,379 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification SystemJahariah Sampe, Masuri OthmanThis paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 2 · 30 Jun 2008 · 7,443 accessesView PDFCite
Research ArticleOpen accessIn the abstractIF-THEN Adder Application in Online DALUT ImplementationMohamed Al Mahdi Eshtawie, Masuri OthmanThis paper presents the application of a proposed if-then rule based adder in implementing distributed arithmetic online lookup table (DALUT). The online DALUT development and implementation is a continuation of our previous work where we proposed this idea and use it in designing finite impulse (FIR) filter. In our LUT architecture we have been able to overcome the major disadvantage … …American Journal of Applied Sciences, Vol. 4, Issue 9 · 30 Sep 2007 · 6,938 accessesView PDFCite
Research ArticleOpen accessIn the abstractAn Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable HardwareAbdellatif Mtibaa, Abdessalem B. Abdelali, Lotfi Boussaid, Elbey BourennaneIn this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. Our objective is to help designers to implement an algorithm in limited FPGA area resources while respecting the execution time constraint. The algorithm to be implemented is represented by a task graph with different implementation alternatives (design points) … …Journal of Computer Science, Vol. 2, Issue 5 · 31 May 2006 · 6,536 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of a Neural Networks Classifier for Face DetectionF. Smach, M. Atri, J. Mitéran, M. AbidFace detection and recognition has many applications in a variety of fields such as security system, videoconferencing and identification. Face classification is currently implemented in software. A hardware implementation allows real-time processing, but has higher cost and time to-market. The objective of this work was to implement a classifier based on neural networks MLP (Multi-layer Perception) for face detection. The … …Journal of Computer Science, Vol. 2, Issue 3 · 31 Mar 2006 · 6,885 accessesView PDFCite