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45 results for “CMOS”
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Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite
Research ArticleOpen accessIn the abstractEffect of Doping Position on the Active Silicon-on-Insulator Micro-Ring Resonator Based on Free Carrier InjectionB. Mardiana, Sahbuddin Shaari, P. Susthitha Menon et al.Problem statement: Metal interconnects have become significant limitation on the scaling of CMOS technologies in electronics integrated circuit. Silicon photonics has offers great potential to overcome this critical bottleneck due to the advantages of optical interconnects. Silicon-based optical micro-ring resonator is promising basic element of future electronic-photonic integrated circuits because of its wide applications on photonic devices such as modulator, … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 9 Aug 2012 · 7,342 accessesView PDFCite
Research ArticleOpen accessIn the abstractA 2-12 GHz Low Noise Amplifier Design for Ultra Wide Band ApplicationsV. Vaithianathan, J. Raja, R. SrinivasanProblem statement: The Low Noise Amplifier (LNA) is a core block of an Ultra Wide Band (UWB) receiver since it amplifies a very weak signal received at the antenna to acceptable levels while introducing less self-generated noise and distortions. The LNA design poses a unique challenge as it requires simultaneous optimization of various performance parameters like power gain, input matching, … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 9 Jun 2012 · 7,397 accessesView PDFCite
Research ArticleOpen accessIn the abstractHigh Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise ReductionT. S. Karthik, V. Jawahar Senthil KumarProblem statement: In any multimedia processor, controller may consume most of the on-chip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications … …Journal of Computer Science, Vol. 8, Issue 3 · 6 Jan 2012 · 7,172 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Capacitance to Voltage Converter for Capacitive Sensor TransducerA.H.M. Zahirul Alam, Nurul Arfah, Sheroz Khan, Md. Rafiqul IslamProblem statement: The design of Capacitance to Voltage Converter (CVC) for capacitive sensor transducer was presented. The proposed design will reduce the size, power consumption and supply voltage of the circuit and can be used in high frequency band transducer. Approach: The design was implemented using the Operational amplifier (Op amp) and capacitive network. The circuit was simulated using the … …American Journal of Applied Sciences, Vol. 7, Issue 10 · 31 Oct 2010 · 8,436 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel High Stop Band All Complementary MOSFET Switched-Capacitor FilterMoussa Abdallah, Ismail NabhanProblem statement: Filters are widely used in various applications including communications, electronics and biomedical engineering. The performance and size of the filter is of interest especially in chip implementation. A switched-capacitor low-pass filter was designed and simulated using a 0.18 μm 1P6M CMOS technology. Approach: This circuit design offered obvious advantages in increasing the stopband attenuation, reducing passband ripple and … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 4 · 31 Dec 2009 · 7,863 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Multi-Valued Quaternary Based Analog-to-Digital ConverterA.H.M. Zahirul Alam, Wahab Adetunji Lawal, Sheroz Khan, Muhammad Mahbubur RashidProblem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC) circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,291 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band ZigbeeNesreen Mahmoud Hammam Ismail, Masuri OthmanProblem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,057 accessesView PDFCite
Research ArticleOpen accessIn the abstractInverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHzMahmoud AbdellaouiProblem statement: In this study and in consequence of the restricted performance of the multi standard wireless receiver utilizing the classical architectures, we proposed and presented a new architecture of multi band wireless receiver based on an Inverse Sine Phase Detector Phase Locked Loop (ISPDPLL) associated with modified multi band LC quadrature Voltage Controlled Oscillator (VCO), supporting GSM/DCS/DECT/Bluetooth/WiMax systems. Approach: … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,251 accessesView PDFCite
Research ArticleOpen accessIn the abstractComparative Studies on the Performance of Low Power Transmitters for Wireless Sensor NodesT. Sasilatha, J. RajaProblem statement: Power consumption was one of the most challenging aspects to design low power wireless sensor nodes. The objectives of the study were to (i) Design low voltage, low power transmitters for wireless sensor nodes and (ii) Compare and analyze the performance of the transmitters. Approach: The transmitters employed direct digital modulation scheme to reduce the power consumption of … …Journal of Computer Science, Vol. 5, Issue 2 · 28 Feb 2009 · 7,450 accessesView PDFCite