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22 results for “high speed architecture”
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Research ArticleOpen accessIn the abstractModelling of Digital Assisted Backend Correction Analogue to Digital Converters with Verilog-AGong Yuehong, Luo Min, Ma JianguoProblem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier … …Current Research in Nanotechnology, Vol. 2, Issue 2 · 3 Sep 2012 · 7,601 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,155 accessesView PDFCite
Research ArticleOpen accessIn the abstractMobility Management for Seamless Information Flow in a Heterogeneous NetworksAdiline Macriga, AnandhakumarProblem statement: In the heterogeneous networks, generally the entire networks operating on the Radio Frequencies under wireless mode available for communication are brought under a single head based on their common operating procedures and functions. As a common mode the basic functions of the networks are requesting, tracing, sending, acknowledging, authenticating, authorizing, receiving, updating, forwarding, controlling, registering, managing. As the … …Journal of Computer Science, Vol. 7, Issue 2 · 25 Feb 2011 · 6,889 accessesView PDFCite
Research ArticleOpen accessIn the abstractOn-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform ArchitectureYazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman et al.Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 30 Nov 2010 · 8,010 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless ReceiversRozita Teymourzadeh, Yazan Samir Algnabi, Masuri Othman et al.Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,815 accessesView PDFCite
Research ArticleOpen accessIn the abstractImproving the Performance of Backpropagation Neural Network Algorithm for Image Compression/Decompression SystemOmaima N.A. AL-AllafProblem statement: The problem inherent to any digital image is the large amount of bandwidth required for transmission or storage. This has driven the research area of image compression to develop algorithms that compress images to lower data rates with better quality. Artificial neural networks are becoming attractive in image processing where high computational performance and parallel architectures are required. … …Journal of Computer Science, Vol. 6, Issue 11 · 26 Oct 2010 · 8,370 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Array -Based System-on-Chip for Real-Time Power Process ControlAhmed Karim Ben Salem, Slim Ben Othman, Slim Ben SaoudProblem Statement: Nowadays Real-Time (RT) embedded control applications require not just higher performance but more flexibility as well without increasing cost and resources. Approach: In this study we presented a promising co-design and implementation of control solution. We developed flexible solution using software control algorithms coupled with an embedded RT kernel on powerful embedded processor cores, combined with reconfigurable logic … …American Journal of Applied Sciences, Vol. 7, Issue 1 · 31 Jan 2010 · 7,455 accessesView PDFCite
Research ArticleOpen accessIn the abstractProtection for an Immediate Split Structure of Tree-Based EPON Architecture-Ideal Condition AnalysisMohammad Syuhaimi Ab-Rahman, Siti Asma Che Aziz, Kasmiran JumariProblem statement: Ethernet Passive Optical Network (EPON) was proposed to overcome the bandwidth bottleneck at the Access Networks due to its simplicity, cost effective and wide spread deployment. A failure in access networks can cause serious problems, because access network transmit aggregated high speed traffic from hundreds of subscribers. Protection and restoration mechanisms have been applied in backbone networks, but … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,276 accessesView PDFCite
Research ArticleOpen accessIn the abstractPower Consumption and Performance’s Library on DSPs: Case Study MPEG2Jalel Ktari, Mohamed Abid, Nathalie Julien, Johann LaurentThe growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area, but also on power throughout the design space exploration. This article presents a high-level design space exploration methodology. It allows … …Journal of Computer Science, Vol. 3, Issue 3 · 31 Mar 2007 · 6,827 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band ZigbeeNesreen Mahmoud Hammam Ismail, Masuri OthmanProblem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,057 accessesView PDFCite