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28 results for “Processor design”
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Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessIn the abstractImplementing a Vector Controller Using 68k ProcessorsMohammad Bagher, Bannae Sharifian, Mohammad Reza Feyzi et al.Problem statement: This study described the design of a 3-phase AC Induction Motor (ACIM) vector control drive with position encoder coupled to the motor shaft. Approach: It was based on free scale's (Motorola's) 68k micro processor devices. Although the free scale 56F80x (56800 core) and 56F8300 (56800E core) families were well-suited for digital motor control and offer all things was … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 7,686 accessesView PDFCite
Research ArticleOpen accessIn the abstractEfficient Reversible Montgomery Multiplier and Its Application to Hardware CryptographyNoor Muhammed Nayeem, Lafifa Jamal, Hafiz Md. Hasan BabuProblem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not … …Journal of Computer Science, Vol. 5, Issue 1 · 31 Jan 2009 · 7,852 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign and Bandwidth Analysis of Fault-Tolerant Multistage Interconnection NetworksR. Aggarwal, L. KaurThe design of a suitable interconnection network for inter-processor communication is one of the key issues of the system performance. In this study a new irregular interconnection network IABN (Irregular Augmented Baseline) has been proposed. IABN is designed by modifying existing ABN (Augmented Baseline Network). ABN is a regular multi-path network with limited fault tolerance. IABN provides three times more … …Journal of Computer Science, Vol. 4, Issue 11 · 30 Nov 2008 · 6,830 accessesView PDFCite
Research ArticleOpen accessIn the abstractDSP-128:Stream Cipher Based On Discrete Log Problem And Polynomial ArithmeticKhaled M. Suwais, Azman SamsudinDSP-128 is a new multithreaded stream cipher based on the intractability of the Discrete Logarithm Problem (DLP) with key size of 128-bit. The design of DSP-128 is divided into three stages: Initialization Stage, Keystream Generation Stage, and Encryption Stage. The design goal of DSP-128 is to come up with a secure stream cipher with good performance for data encryption. The … …American Journal of Applied Sciences, Vol. 5, Issue 7 · 31 Jul 2008 · 7,396 accessesView PDFCite
Research ArticleOpen accessIn the abstractDynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing ArchitecturesN. Ramadass, S. Natarajan, J. Raja Paul PerinbamEmerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic … …Journal of Computer Science, Vol. 3, Issue 10 · 31 Oct 2007 · 6,727 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS TechnologySiva Kumar Palaniappan, Tun Zainal Azni ZulkifliThis paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes … …American Journal of Applied Sciences, Vol. 4, Issue 8 · 31 Aug 2007 · 7,164 accessesView PDFCite
Research ArticleOpen accessIn the abstractComputer Simulator: An Educational Tool for Computer ArchitectureMihyar HessonThe great advancement in computer architecture and cache memory design and technology had a considerable influence on the way computer architecture was taught in universities. This requires students to be able to visualize the detailed activities that take place within a computer processor and its interaction with memory system. Computer simulators could effectively be used to enhance the understanding and … …American Journal of Applied Sciences, Vol. 3, Issue 11 · 30 Nov 2006 · 7,468 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of a Merged DSP Microcontroller for Embedded Systems using Discrete Orthogonal TransformA. K. Rath, P. K. MeherIn this paper we have proposed the design of a DSP microcontroller where the processor load is significantly reduced by relegating the math-intensive DSP algorithm to dedicated transform computing modules. It is shown that the use of such transform modules will facilitate scalability, reusability and flexibility for implementation of wide varieties of DSP functionalities. Moreover, it would be possible to … …Journal of Computer Science, Vol. 2, Issue 5 · 31 Aug 2006 · 6,918 accessesView PDFCite
Research ArticleOpen accessIn the abstractHighly Efficient Elliptic Curve Crypto-Processor with Parallel GF(2m) Field MultipliersTurki F. Al-Somani, M. K. Ibrahim, Adnan GutubThis study presents a high performance GF(2m) Elliptic Curve Crypto-processor architecture. The proposed architecture exploits parallelism at the projective coordinate level to perform parallel field multiplications. In the proposed architecture, normal basis representation is used. Comparisons between the Projective, Jacobian and Mixed coordinate systems using sequential and parallel designs are presented. Results show that parallel designs using normal basis gives … …Journal of Computer Science, Vol. 2, Issue 5 · 31 May 2006 · 6,874 accessesView PDFCite