29 results for “Integrated Circuit (IC)”

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Research ArticleOpen accessIn the abstractMulticore Based Open Loop Motor Controller Embedded System for Permanent Magnet Direct Current MotorK. Baskaran, K.S. Vijula GraceProblem statement: In an advanced electronics world most of the applications are developed by microcontroller based embedded system. Approach: Multicore processor based motor controller was presented to improve the processing speed of the controller and improve the efficiency of the motor by maintaining constant speed. It was based on the combination of Cortex processor (Software core) and Field Programmable Gate … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 22 Mar 2012 · 7,035 accessesView PDF Cite

Research ArticleOpen accessIn the abstractAn Optimized Device Sizing of Analog Circuits using Particle Swarm OptimizationP. Prem Kumar, K. DuraiswamyProblem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.). For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most … …Journal of Computer Science, Vol. 8, Issue 6 · 19 Mar 2012 · 7,769 accessesView PDF Cite

Research ArticleOpen accessIn the abstractField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDF Cite

Research ArticleOpen accessIn the abstractEfficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAsMohammed H. Al MijalliProblem statement: The S-Box transformation is a computationally intensive and important operation of the Advanced Encryption Standard (AES). Approach: This study presents the comparative study between reduced Residue of Prime Numbers and Galois Filed GF (28) based SBoxes using Virtex-5 and Virtex-6 FPGA devices. The implementation of S-Boxes is done using Very High speed integrated circuit Hardware Description Language (VHDL). … …American Journal of Applied Sciences, Vol. 8, Issue 8 · 18 Jul 2011 · 6,975 accessesView PDF Cite

Research ArticleOpen accessIn the abstractModeling of Piezoelectric Actuators Based on Bayesian Regularization Back Propagation Neural NetworkWen Wang, Zhu Zhu, Yanding Wei, Zichen ChenProblem statement: Piezoelectric actuator is a kind of key driving components for micropositioning stages, micropumps, micro valves, micro gripper and so on in the fields of micro/nano technology such as integrated circuit manufacturing, precision instruments, ultra precision fabrication, biomedical manipulation. It has lots of advantages including high stiffness, fast response times, less heat generating, low power consumption and large force … …Current Research in Nanotechnology, Vol. 1, Issue 1 · 15 Jun 2011 · 7,059 accessesView PDF Cite

Research ArticleOpen accessIn the abstractDesign and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley MultipliersMuhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar, Fahad K. Al-HusseinProblem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 2 · 30 Jun 2010 · 8,123 accessesView PDF Cite

Research ArticleOpen accessIn the abstractHardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA DevicesMuhammad H. RaisProblem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,334 accessesView PDF Cite

Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDF Cite

Research ArticleOpen accessIn the abstractA Novel High Stop Band All Complementary MOSFET Switched-Capacitor FilterMoussa Abdallah, Ismail NabhanProblem statement: Filters are widely used in various applications including communications, electronics and biomedical engineering. The performance and size of the filter is of interest especially in chip implementation. A switched-capacitor low-pass filter was designed and simulated using a 0.18 μm 1P6M CMOS technology. Approach: This circuit design offered obvious advantages in increasing the stopband attenuation, reducing passband ripple and … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 4 · 31 Dec 2009 · 7,863 accessesView PDF Cite

Research ArticleOpen accessIn the abstractDesign of Multi-Valued Quaternary Based Analog-to-Digital ConverterA.H.M. Zahirul Alam, Wahab Adetunji Lawal, Sheroz Khan, Muhammad Mahbubur RashidProblem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC) circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,291 accessesView PDF Cite