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19 results for “Digital hardware implementation”
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Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Software Agent for Speech Abiding SystemsR. Manoharan, K. Vivekanandan, V. SundaramProblem statement: In order to bring speech into the mainstream of business process an efficient digital signal processor is necessary. The Fast Fourier Transform (FFT) and the butter fly structure symmetry will enable the harwaring easier. With the DSP and software proposed, togetherly established by means of a system, named here as “Speech Abiding System (SAS)”, a software agent, which … …Journal of Computer Science, Vol. 5, Issue 2 · 28 Feb 2009 · 7,744 accessesView PDFCite
Research ArticleOpen accessIn the abstractImplementation of Low-Memory Reference FFT on Digital Signal ProcessorYi-Pin Hsu, Shin-Yu LinProblem statement: In order to improve and implement Fast Fourier Transform (FFT), in general, an efficient parallel form in digital signal processor is necessary. The butterfly structure is an important role in FFT, because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even … …Journal of Computer Science, Vol. 4, Issue 7 · 31 Jul 2008 · 7,142 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordSoftware Defined Radio Implementation of a QPSK Modulator/Demodulator in an Extensive Hardware Platform Based on FPGAs Xilinx ZYNQSérgio Bimbi Junior, Vitor Chaves de Oliveira, Gunnar Bedicks JuniorSoftware Defined Radio (SDR) technology enables wireless devices deployment with support to multiple interfaces in modulation formats and it has gained importance due to the current wireless standards proliferation. In order to activate these functionalities it is necessary to apply SDR inside a reconfigurable hardware such as the Field Programmable Gate Array (FPGA). In this study, design procedures developments are … …Journal of Computer Science, Vol. 11, Issue 4 · 2 Jun 2015 · 8,813 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordSpartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay StudyMohammed H. Al MijalliProblem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be … …American Journal of Applied Sciences, Vol. 8, Issue 6 · 13 Jun 2011 · 6,428 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordDesign and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley MultipliersMuhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar, Fahad K. Al-HusseinProblem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 2 · 30 Jun 2010 · 8,123 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordDesign and Implementation of an Optimal Fuzzy Logic Controller Using Genetic AlgorithmS. Khan, S. F. Abdulazeez, L. W. Adetunji et al.All control systems suffer from problems related to undesirable overshoot, longer settling times and vibrations while going form one state to another state. Most of relevant techniques had been in the form of suggesting modification and improvement in the instrumentation or interfacing part of the control system and the results reported, remain suffering from shortcomings related to hardware parameter dependence … …Journal of Computer Science, Vol. 4, Issue 10 · 31 Oct 2008 · 8,049 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordDesign of a Merged DSP Microcontroller for Embedded Systems using Discrete Orthogonal TransformA. K. Rath, P. K. MeherIn this paper we have proposed the design of a DSP microcontroller where the processor load is significantly reduced by relegating the math-intensive DSP algorithm to dedicated transform computing modules. It is shown that the use of such transform modules will facilitate scalability, reusability and flexibility for implementation of wide varieties of DSP functionalities. Moreover, it would be possible to … …Journal of Computer Science, Vol. 2, Issue 5 · 31 Aug 2006 · 6,918 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordCodesign Methodology of Real-time Embedded Controllers for Electromechanical SystemsSlim Ben Saoud, Andreas Gerstlauer, Daniel D. GajskiUnder increasing time-to-market pressures in the electric drives industries, the development time of new algorithms and new control systems including their debugging time must be minimized. This requirement can be satisfied only by using a well-defined system-level design methodology and by reducing the migration time between the algorithm development language and the hardware specification language. In this study, we propose … …American Journal of Applied Sciences, Vol. 2, Issue 9 · 30 Sep 2005 · 6,444 accessesView PDFCite