Design of a High-Performance IP Switching Architecture

In this study we present the architecture for use in high-performance switching networks with support quality of service (QoS) guarantees. Quality of services guarantees in terms of delay, through-put and loss rate can be provided by using mechanism's support like scheduling and buffer management at switching architecture in packet switching networks. Our architecture is based on a new data structure for the scheduling and memories management which is the circular linked list and the pipeline for the active queues elements. In addition to being very fast, the architecture also scales very well to a large number of priority levels and to large queue size. We give a detailed description of the block that support QoS guarantees. However our proposed architecture is composed of three parts: input controller, backplane and output controller. And we give the corresponding algorithms and the corresponding implementation of this architecture.